1) Field of the Invention
The present invention relates to test methodology in general and in particular to structures and methodologies used in boundary scan to test the connectivity of interconnected devices.
2) Prior Art
Boundary scan testing to detect defects in the connectivity of connected devices are well known in the prior art. IEEE 1149.1 standard also called JTAG set forth the popular and well known prior art technique for boundary scan testing. The JTAG structure requires an on chip controller (state machine). The on chip controller uses silicon real estate (space), a scarce commodity in semiconductor integrated circuit technology.
FIG. 1 shows a prior art chip 100 configured according to JTAG standard. The prior art chip consists of internal circuits 102 connected to JTAG boundary scan cells 104, I/O drivers/receivers 106 and I/O pads 108. As can be seen from the FIG. 1 each one of the boundary scan cells 104 (JTAG structure) is placed in series with its associated driver/receiver circuit. Stated another way each of the boundary scan cells is placed between its associated I/O driver/receiver and the internal logic. By so doing the signal path used by the chip during normal operation and the test signal path coalesce.
Even though the JTAG structure and test methodology works well for their intended purposes they include features which make them undesirable. As pointed out above, the JTAG structures are placed within the normal signal patch of the chip resulting in a finite timing delay. This is undesirable in that it slows down the speed of the chip. As pointed out above the on chip controller required by JTAG structures is another negative. Still another drawback is that JTAG structure and methodology has limited testing capabilities. It cannot test certain types of differential and analog I/Os.
In view of the above there is a need for a structure and methodology for boundary scan testing that solves problems and shortcomings identified with prior art JTAG or IEEE 1149.1 standard or other conventional Boundary Scan testing methodology. This need is met by the structure and methodology of the present invention set forth and described hereinafter.